This invention relates to an inverter circuit, and more particularly to an inverter circuit composed of bipolar transistors.
As is well known, inverter circuits are widely used in integrated circuits (hereinafter abbreviated as IC's). Recently, in accordance with great increase in capacity of monolithic bipolar IC's, an operating energy level handled in IC's is being reduced whether they are for logic use or for memory use, and consequently, between the inside and the outside of an IC a difference in energy levels of the respective logic circuits is being increased. More particularly, inside of an IC, as the size of elements and wirings comprised therein is reduced, a current mode logic (hereinafter abbreviated as CML) is widely used because of its operating at a low energy level (in general about 2 volts) and a flexibility in design. While, outside of the IC, a transistor-transistor logic (hereinafter abbreviated as TTL) that operates at a high energy level (in general about 5-6 volts) and has a generality in wide application is widely used. Therefore for transferring logic information from the inside to the outside of IC, a level conversion circuit is necessitated for converting the CML logic level inside of the IC into the TTL logic level outside of the IC.
As the above-referred level conversion circuit, an inverter circuit composed of bipolar transistors has been mainly utilized. A variety of efforts have been made to improve operation speed of such inverter circuit. In order to realize a high speed operation, every transistor has been operated in a non-saturating mode. For this purpose, clamping transistor with a Schottky diode or various circuit arrangements for preventing the saturation has been utilized. Among the transistors to be prevented from saturation as described above, the inverter transistor in the final output stage has especially little tolerance in design. Normally, an output of a TTL is rated, for example, by a collector current of the final stage inverter transistor as high as 16 mA and a very small value of the collector-emitter voltage such as 0.4 volts. For the purpose of operating such an inverter transistor so as to be adapted for a high speed operation, though a method for preventing saturation by reducing a resistance loss in a collector of the transistor, namely by enlarging the dimension of the transistor, has been known, this is almost impossible in view of the fact that the capacitance of the output terminal is required to be as small as possible. In addition, though a method of reducing the resistance value of a pull-down resistor connected in parallel to the base-emitter circuit in order to lower a discharge impendance on the base side at the off-state of the inverter transistor has been known, this results in increase of a power consumption and lowers the operation speed upon on-state of the inverter transistor on the contrary to the desired purpose.
It is one object of the present invention to provide an inverter circuit composed of bipolar transistors which has a high power consumption efficiency, and which can operate at a high speed.
Another object of the present invention is to provide an inverter circuit having a level conversion capability which can operate at a high speed.